1. Field of the Invention
The present invention relates generally to BiCMOS semiconductor fabrication methods and multilayer structures resulting from such methods. More particularly, the present invention relates to a method for preventing over-etching during BiCMOS fabrication without adding additional fabrication steps.
2. State of the Art
Semiconductor devices fabricated using CMOS and bipolar techniques have been used for decades to manufacture various electrical components. More recently hybrid semiconductor devices, fabricated using techniques known as BiCMOS processes, have been developed to combine the relatively high speed bipolar devices with the high density CMOS devices on a common substrate. BiCMOS devices are especially desirable as memory devices wherein high output bipolar drivers can be coupled with low power consumption CMOS memories.
Initially BiCMOS fabrication was achieved by performing all of the conventional process steps for both bipolar devices and CMOS devices. A bipolar device fabrication process is described in an article "An Advanced Bipolar Transistor With Self-Aligned Ion-Implanted Base and W/Poly Emitter", Chen et at., IEEE Transactions On Electron Devices, Vol. 35, No. 8, Aug. 1988. This resulted in a relatively costly manufacturing process which was susceptible to low yield due to the large number of process steps and increased likelihood of manufacturing errors. More recent efforts have been directed to integrating the bipolar fabrication process with the CMOS fabrication process by reducing the total number of process steps (e.g., masking steps).
One result of this consolidation of steps is that the gates of the CMOS devices and the emitters of the bipolar devices are often formed during a single step of depositing a polysilicon layer across the entire semiconductor surface. As described in more detail below, the polysilicon in the gate areas is deposited on a gate oxide layer overlying the silicon substrate. In the emitter areas of the bipolar transistors, however, the polysilicon is deposited directly on the epitaxial silicon since earlier fabrication steps require that the gate oxide in those areas be removed.
Next, the polysilicon is etched away from surface areas not designated as gates or emitters. In the gate areas, this presents no difficulties because the gate oxide under the polysilicon acts as a detectable end-point which indicates when etching should be discontinued to avoid etching the underlying epitaxial silicon. In the emitter areas, however, the interface between the polysilicon used to form the emitter and the epitaxial substrate (single crystalline silicon) is not readily detectable as an end-point. The effort to reduce the number of BiCMOS processing steps has resulted in avoiding the use of any readily detectable end-point material between the emitter polysilicon and the epitaxial base. Thus, etching often continues past the polysilicon layer and into the epitaxial silicon.
This over-etching reduces the vertical dimension of a bipolar transistor's extrinsic base which is formed in the epitaxial substrate beneath the emitter. Because the extrinsic base is typically formed with an exemplary vertical depth of only about a few thousand angstrom, such over-etching can result in a base which experiences electrical leakage during operation of the bipolar transistor and which undermines performance of the BiCMOS device. Nonetheless, such over-etching has been considered an acceptable design tradeoff given the other advantages of BiCMOS devices and the need to simplify the overall fabrication process.